testsuite/synth/issue1460/rightmost02.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rightmost02 is
  port (d : signed (2 to 4);
        res : out integer);
end rightmost02;

architecture behav of rightmost02 is
begin
  res <= find_rightmost (d, '1');
end behav;