testsuite/synth/issue1460/leftmost02.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity leftmost02 is
  port (d : signed (8 to 12);
        res : out integer);
end leftmost02;

architecture behav of leftmost02 is
begin
  res <= find_leftmost (d, '1');
end behav;