testsuite/synth/issue1428/repro4.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

library ieee;
use ieee.std_logic_1164.all;

entity repro4 is
  port (a : out std_logic;
        b : std_logic_vector(7 downto 0));
end;

architecture behav of repro4 is
  signal s : std_logic_vector(7 downto 0);
begin
  s <= b;
  a <= '1' when s /= x"00" else '0';

  s (3) <= '0';
  s (5) <= '0';
end behav;