blob: a75a10f9b5f0b7b7bbd21b12eab8f1b3cad93526 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bar is
generic(
Clk_freq : integer := 50;
Bit_rate : integer := 460800
);
port (
rst_i : in std_logic;
clk_i : in std_logic;
start_i : in std_logic;
output : out std_logic_vector(5 downto 0)
);
end bar;
architecture bar of bar is
constant Freq_ratio : integer := Clk_freq*(10**6)/Bit_rate;
signal period_counter : std_logic_vector(5 downto 0);
signal res : std_logic_vector(5 downto 0);
begin
counter: process(rst_i, clk_i)
begin
if rst_i = '1' then
period_counter <= (others => '0');
elsif rising_edge(clk_i) then
if start_i = '1' then
if period_counter /= freq_ratio - 1 then
period_counter <= period_counter + 1;
else
period_counter <= (others => '0');
end if;
else
period_counter <= (others => '0');
end if;
end if;
end process;
result: process(rst_i, clk_i)
begin
if rst_i = '1' then
res <= conv_std_logic_vector(0, 6);
elsif rising_edge(clk_i) then
if start_i = '1' then
res <= period_counter;
else
res <= conv_std_logic_vector(0, 6);
end if;
end if;
end process;
output <= res;
end bar;
|
