testsuite/synth/issue1319/repro3.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;

entity repro3 is
	port (
		i : in std_ulogic_vector(1 downto 0);
                o : out std_ulogic_vector (3 downto 0)
	);
end entity repro3;

architecture behav of repro3 is
    function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
    begin
       case v is
       when "01" =>
         null;
       when others =>
         return "0000";
       end case;
       return "1111";
    end;
begin
  o <= func (i);
end architecture behav;