testsuite/synth/issue1271/issue3.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity issue is
    port
      (i_foo : in  std_logic;
       o_foo : out std_logic);
end entity issue;

architecture beh of issue is
    signal k_foo  : std_logic := i_foo;
begin
    o_foo <= k_foo xor '0';
end architecture;