testsuite/synth/issue1258/ent.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

-- count number of '1'.
library ieee;
use ieee.std_logic_1164.all;
entity ent is
  port    (
    sel   : in  std_ulogic;
    din   : in  std_ulogic_vector(15 downto 0);
    dout  : out std_ulogic
  );
end;

architecture rtl of ent is
begin
  comb : process (sel, din)
    variable v : std_ulogic;
  begin
    v := '0';
    if sel = '1' then
      for i in din'range loop
        if din(i) = '0' then
          next;
        end if;
        v := not v;
      end loop;
    end if;
    dout <= v;
  end process;
end;