testsuite/synth/issue1240/tb_issue3.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

entity tb_issue3 is
end tb_issue3;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture behav of tb_issue3 is
  signal i : integer := 0;
  signal o : signed (3 downto 0);
begin
  dut: entity work.issue3
    port map (i, o);

  process
  begin
    i <= 0;
    wait for 1 ns;
    assert o = "0010" severity failure;

    i <= 1;
    wait for 1 ns;
    assert o = "0011" severity failure;

    i <= -1;
    wait for 1 ns;
    assert o = "0001" severity failure;

    wait;
  end process;
end behav;