testsuite/synth/issue1231/top3.vhdl


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entity top3 is
  generic (
    ok : boolean := false
    );
    port (
        clk : in bit;
        inp : in bit;
        outp : out bit);
end;

architecture beh of top3 is
begin
  assert ok report "my assert message, value:" & bit'image(inp);
  outp <= inp;
end beh;