testsuite/synth/issue1231/top2.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

entity top2 is
  generic (
    ok : boolean := false
    );
    port (
        clk : in bit;
        inp : in bit;
        outp : out bit);
end;

architecture beh of top2 is
begin
  assert ok report "my assert message";
  outp <= inp;
end beh;