testsuite/synth/issue1199/issue2.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14

library IEEE;
use IEEE.std_logic_1164.all;

entity issue2 is
 port(
  a : in  std_logic_vector(7 downto 0);
  b : out std_logic_vector(2 downto 0)
 );
end issue2;

architecture behavior of issue2 is
begin
    b <= a;
end behavior;