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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counters_7 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counters_7;
architecture archi of counters_7 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
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