testsuite/synth/issue1186/ent.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity ent is
end;

architecture a of ent is
    component c is
        generic (
            G_REAL : real
        );
    end component;
begin
    c_inst: c generic map (G_REAL => 1.5);
end;