testsuite/synth/issue1153/ent.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14

library ieee;
use ieee.std_logic_1164.all;

entity ent is
	port (
		a, b : in std_logic;
		q : out std_logic
	);
end;

architecture a of ent is
begin
	q <= a xnor b;
end;