testsuite/synth/issue1082/ent.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
  port(
    a_in  : in std_logic_vector(31 downto 0);
    b_out : out std_logic_vector(31 downto 0)
  );
end test;

architecture rtl of test is
begin
  process(all)
  begin
    b_out <= std_logic_vector(to_unsigned((31-to_integer(unsigned(a_in))) / 4, 32));
  end process;
end;