testsuite/synth/issue1034/ent.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14

use work.p.all;

entity ent is
	generic (
		WIDTH : natural := 8
	);
	port (
		test : in bit_vector(id(WIDTH)-1 downto 0)
	);
end ent;

architecture a of ent is
begin
end a;