blob: 21615615b09f52b74746401d4f63c720d1f7bfaf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
|
entity tb_forgen02 is
end tb_forgen02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forgen02 is
signal a : std_logic_vector (7 downto 0);
begin
dut: entity work.forgen02
port map (a);
process
begin
wait for 1 ns;
assert a = x"00" severity failure;
wait;
end process;
end behav;
|
