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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity external02_sub is
port (clk : std_logic;
rst : std_logic;
a : std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0));
end external02_sub;
architecture behav of external02_sub is
signal accum : std_logic_vector(7 downto 0);
begin
process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
accum <= (others => '0');
else
accum <= std_logic_vector(unsigned(accum) + unsigned(a));
end if;
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
o <= (others => '0');
else
o <= accum;
end if;
end if;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity external02 is
port (clk : std_logic;
rst : std_logic;
a : std_logic_vector(7 downto 0);
accum : out std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0));
end external02;
architecture behav of external02 is
component external02_sub is
port (
clk : std_logic;
rst : std_logic;
a : std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0));
end component external02_sub;
begin
dut : external02_sub
port map (clk => clk,
rst => rst,
a => a,
o => o);
accum <= << signal .external02.dut.accum : std_logic_vector(7 downto 0) >>;
end behav;
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