testsuite/synth/exit01/exit01.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

library ieee;
use ieee.std_logic_1164.all;

entity exit01 is
  port (val : std_logic_vector (3 downto 0);
        res : out integer);
end exit01;

architecture behav of exit01 is
begin
  process(val)
  begin
    res <= 4;
    for i in val'reverse_range loop
      if val (i) = '1' then
        res <= i;
        exit;
      end if;
    end loop;
  end process;
end behav;