testsuite/synth/dispin01/rec02.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;

entity rec02 is
  port (inp : myrec;
        o : out std_logic);
end rec02;

architecture behav of rec02 is
begin
  o <= inp.b when inp.a > 3 else '0';
end behav;