testsuite/synth/dispin01/rec01.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;

entity rec01 is
  port (inp : myrec;
        o : out std_logic);
end rec01;

architecture behav of rec01 is
begin
  o <= inp.a or inp.b;
end behav;