testsuite/synth/dff03/dff01.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

library ieee;
use ieee.std_logic_1164.all;

entity dff01 is
  port (q : out std_logic;
        d : std_logic;
        en1 : std_logic;
        en2 : std_logic;
        clk : std_logic);
end dff01;

architecture behav of dff01 is
begin
  process (clk) is
  begin
    if en1 = '1' and rising_edge (clk) then
      q <= d;
    end if;
  end process;
end behav;