testsuite/synth/dff01/dff03.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

library ieee;
use ieee.std_logic_1164.all;

entity dff03 is
  port (q : out std_logic_vector(7 downto 0);
        d : std_logic_vector(7 downto 0);
        clk : std_logic);
end dff03;

architecture behav of dff03 is
begin
  process (clk) is
  begin
    if rising_edge (clk) then
      q <= d;
    end if;
  end process;
end behav;