blob: af208cf4481a674c7d52297202067701df2e6f15 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
library ieee;
use ieee.std_logic_1164.all;
entity mand is
port (v : std_logic_vector (7 downto 0);
b : std_logic;
r : out std_logic_vector (7 downto 0));
end mand;
architecture behav of mand is
begin
process (v, b)
begin
for i in v'range loop
r(i) <= v (i) and b;
end loop;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity comp04 is
port (v : std_logic_vector (7 downto 0);
r : out std_logic_vector (7 downto 0));
end;
architecture behav of comp04 is
component mand is
port (
b : std_logic;
v : std_logic_vector (7 downto 0);
r : out std_logic_vector (7 downto 0));
end component;
begin
dut : mand
port map (v => v,
b => v(0),
r => r);
end behav;
|
