testsuite/synth/comp02/mixer.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

library ieee;
use ieee.std_logic_1164.all;

entity mixer is
  port (h, l : std_logic_vector(7 downto 0);
        o : out std_logic_vector (7 downto 0));
end mixer;

use work.pkg.all;
architecture behav of mixer is
  signal t1 : std_logic_vector (7 downto 0);
begin
  a1: cmask
    generic map (mask => x"0f")
    port map (l, t1);
  o <= t1 or h;
end behav;