blob: b7abd8c90e89bcba6cb6fcd59d5271a08d0b2d08 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
entity tb_cnt02 is
end tb_cnt02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt02 is
signal clk : std_logic;
signal rst : std_logic;
signal low : std_logic;
begin
dut: entity work.cnt02
port map (clk => clk, rst => rst, low => low);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert low = '0' severity failure;
rst <= '0';
pulse;
assert low = '0' severity failure;
pulse;
assert low = '0' severity failure;
pulse;
assert low = '0' severity failure;
pulse;
assert low = '1' severity failure;
pulse;
assert low = '1' severity failure;
wait;
end process;
end behav;
|