blob: f66569dbf6ba01a814e8b8fa7697db88a198c448 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
|
library ieee;
use ieee.std_logic_1164.all;
entity case06 is
port (
a : in std_logic;
b : out std_logic
);
end entity;
architecture a of case06 is
begin
process(a)
begin
case a is
when '0' =>
b <= '0';
when 'L' =>
b <= '1';
when others =>
b <= 'Z';
end case;
end process;
end architecture;
|
