testsuite/synth/case01/case03.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity case03 is
  port (a : std_logic_vector (4 downto 0);
        o : out std_logic);
end case03;

architecture behav of case03 is
begin
  with a select o <=
    '0' when others;
end behav;