testsuite/gna/issue71/repro1.vhdl


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entity repro1 is
end repro1;

architecture behav of repro1 is
  signal s1, s2 : bit;

  component comp port (i : in bit; o : out bit);
  end component;
begin

  s1 <= '1';

  c : comp port map (i => s1, o => s2);
end behav;