blob: 83aecf543cb2788ce8f61e5e4b93f7d3ee2007e2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
|
