blob: 0ae81ed9620a6008c31264e1f9f086491e10afb3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (all)
begin
Y <= '1' when Clk = '1' else '0' ;
end process ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
