testsuite/gna/issue2307/repro.vhdl


1
2
3
4
5
6
7
8
9
10
11

library ieee;
use ieee.std_logic_1164.all;

entity repro is
end;

architecture behav of repro is
  constant c : bit := '0';
  signal s : std_logic := to_X01(c);
begin
end behav;