testsuite/gna/issue2065/repro.vhdl


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entity repro is
  generic (depth : natural := 5);
   port (inp : bit := '0');
end entity;

architecture mult of repro is
   signal  s : bit;
begin
  gen: if depth > 0 generate
    inst : entity work.repro
      generic map (depth => depth - 1)
      port map(inp => s and inp);
  end generate;
end architecture mult;