testsuite/gna/issue1697/e2.vhdl


1
2
3
4
5
6
7
8
9
10
11

library ieee;
use ieee.std_logic_1164.all;

entity e is
    port (o : out std_logic_vector(2 downto 0));
end entity;

architecture a of e is
begin
    o <= ('1','0');
end architecture;