testsuite/gna/bug044/aggr2.vhdl


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entity aggr2 is
end;

architecture behav of aggr2 is
  constant g : natural := 1;
begin
  process
    variable v : bit_vector(3 downto 0);
  begin
     v (g + 2 downto g) := (2 downto 0 => '1');
     wait;
  end process;
end;