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/* Definitions for specs for vhdl.
   Copyright (C) 2002
   Free Software Foundation, Inc.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

/* This is the contribution to the `default_compilers' array in gcc.c for
   GHDL.  */

  {".vhd", "@vhdl", 0, 0, 0},
  {".vhdl", "@vhdl", 0, 0, 0},
  {"@vhdl",
   "ghdl1 %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}", 0, 0, 0},
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-09 11:35:56 +0000
: fsm_using_always.v //----------------------------------------------------- module fsm_using_always ( clock , // clock reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; //-------------Output Ports---------------------------- output gnt_0,gnt_1; //-------------Input ports Data Type------------------- wire clock,reset,req_0,req_1; //-------------Output Ports Data Type------------------ reg gnt_0,gnt_1; //-------------Internal Constants-------------------------- parameter SIZE = 3 ; parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ; //-------------Internal Variables--------------------------- reg [SIZE-1:0] state ;// Seq part of the FSM reg [SIZE-1:0] next_state ;// combo part of FSM //----------Code startes Here------------------------ always @ (state or req_0 or req_1) begin : FSM_COMBO next_state = 3'b000; case(state) IDLE : if (req_0 == 1'b1) begin next_state = GNT0; end else if (req_1 == 1'b1) begin next_state= GNT1; end else begin next_state = IDLE; end GNT0 : if (req_0 == 1'b1) begin next_state = GNT0; end else begin next_state = IDLE; end GNT1 : if (req_1 == 1'b1) begin next_state = GNT1; end else begin next_state = IDLE; end default : next_state = IDLE; endcase end //----------Seq Logic----------------------------- always @ (posedge clock) begin : FSM_SEQ if (reset == 1'b1) begin state <= #1 IDLE; end else begin state <= #1 next_state; end end //----------Output Logic----------------------------- always @ (posedge clock) begin : OUTPUT_LOGIC if (reset == 1'b1) begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end else begin case(state) IDLE : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end GNT0 : begin gnt_0 <= #1 1'b1; gnt_1 <= #1 1'b0; end GNT1 : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b1; end default : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end endcase end end // End Of Block OUTPUT_LOGIC endmodule // End of Module arbiter
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-09 11:35:56 +0000