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# =============================================================================
# ____ _ _ ____ _ _
# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___
# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_| |___/
# =============================================================================
# Authors:
# Patrick Lehmann
#
# Package module: DOM: Interface items (e.g. generic or port)
#
# License:
# ============================================================================
# Copyright (C) 2019-2021 Tristan Gingold
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
from typing import List, Iterator
from pydecor import export
from pyVHDLModel.VHDLModel import (
EntitySymbol as VHDLModel_EntitySymbol,
SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol,
ConstrainedScalarSubTypeSymbol as VHDLModel_ConstrainedScalarSubTypeSymbol,
ConstrainedCompositeSubTypeSymbol as VHDLModel_ConstrainedCompositeSubTypeSymbol,
EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol,
SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol,
IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol,
Constraint,
Name,
)
from pyGHDL.libghdl._types import Iir
from pyGHDL.dom import DOMMixin
from pyGHDL.dom._Utils import GetNameOfNode
from pyGHDL.dom.Range import Range
__all__ = []
@export
class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin):
def __init__(self, node: Iir, entityName: str):
super().__init__(entityName)
DOMMixin.__init__(self, node)
@export
class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol, DOMMixin):
def __init__(self, node: Iir, literalName: str):
super().__init__(symbolName=literalName)
DOMMixin.__init__(self, node)
@export
class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol, DOMMixin):
def __init__(self, node: Iir, subTypeName: Name):
if isinstance(subTypeName, (List, Iterator)):
subTypeName = ".".join(subTypeName)
super().__init__(subTypeName=subTypeName)
DOMMixin.__init__(self, node)
@export
class ConstrainedScalarSubTypeSymbol(
VHDLModel_ConstrainedScalarSubTypeSymbol, DOMMixin
):
def __init__(self, node: Iir, subTypeName: str, range: Range = None):
super().__init__(subTypeName=subTypeName, range=range)
DOMMixin.__init__(self, node)
@classmethod
def parse(cls, node: Iir):
pass
@export
class ConstrainedCompositeSubTypeSymbol(
VHDLModel_ConstrainedCompositeSubTypeSymbol, DOMMixin
):
def __init__(
self, node: Iir, subTypeName: str, constraints: List[Constraint] = None
):
super().__init__(subTypeName=subTypeName, constraints=constraints)
DOMMixin.__init__(self, node)
@classmethod
def parse(cls, node: Iir):
pass
@export
class SimpleObjectOrFunctionCallSymbol(
VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin
):
@classmethod
def parse(cls, node: Iir):
name = GetNameOfNode(node)
return cls(name)
@export
class IndexedObjectOrFunctionCallSymbol(
VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin
):
def __init__(self, node: Iir, name: str):
super().__init__(objectName=name)
DOMMixin.__init__(self, node)
@classmethod
def parse(cls, node: Iir):
from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameFromNode
name = GetNameFromNode(node)
return cls(node, name)
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