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* trans-chap4: add commentsTristan Gingold2021-05-161-0/+4
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* grt-table.adb: avoid overflow for computing memory size. For #1761Tristan Gingold2021-05-151-5/+8
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* trans-chap6: handle alias of unbounded record. For #641Tristan Gingold2021-05-131-1/+2
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* ortho: fix CFLAGS/CXXFLAGS distinctionXiretza2021-05-101-1/+1
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* ortho: use LDFLAGS and prefer them over defaultsXiretza2021-05-107-9/+8
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* grt/Makefile: use CFLAGSXiretza2021-05-101-2/+2
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* grt: fix warning about possible constant declarationXiretza2021-05-101-1/+1
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* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
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* std_names: add full and parallel case.Tristan Gingold2021-05-072-3/+7
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* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-072-1/+26
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* netlists-cleanup: do not remove self-assigned output gateTristan Gingold2021-05-071-23/+30
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* vhdl-sem_stmts: handle aliases for force/release assignment. Fix #1751Tristan Gingold2021-05-061-5/+8
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* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
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* ghdlsynth: never display a foreign module as pure vhdlTristan Gingold2021-04-281-2/+7
| | | | (do not try to display the original entity when this is none)
* synth: add verilog outputTristan Gingold2021-04-283-0/+1423
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* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-2814-45/+49
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* synth: use a generic version of synth-environment.Tristan Gingold2021-04-2718-363/+479
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* Migrate deprecated DebugLoc::get to DILocation::getJeroen Van den Keybus2021-04-271-4/+4
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* synth-insts.adb: avoid a crash after an error during instantiation. Fix #1734Tristan Gingold2021-04-232-1/+9
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* move ghwlib and ghwdump sources to subdir 'ghw'umarcor2021-04-233-3020/+0
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* Makefile: add and use all.ghw, install.ghw and uninstall.ghw targetsumarcor2021-04-231-10/+0
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* src: Minor clarifications in Error messages for Warning and VHDL std options.Ondrej Ille2021-04-221-4/+6
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* grt: Use GRTs sort for dump table.Ondrej Ille2021-04-221-9/+19
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* grt-avls: optimize, disable debug check after insertMartin Jeřábek2021-04-221-4/+4
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* grt: optimize wave dumpMartin Jeřábek2021-04-224-11/+49
| | | | | | | | Instead of walking through all the signals every cycle, keep an array of changed signals (without duplicates). Before dumping, sort the array. Afterwards clear it. This massively improves performance on big designs.
* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
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* synth-vhdl_oper.adb: adjust previous patch and testTristan Gingold2021-04-211-1/+12
| | | | | resize with two signed parameters extract the size of the second parameter to resize the first one.
* synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731Tristan Gingold2021-04-211-0/+1
| | | | With an hint from T.Meissner
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-2115-124/+193
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* VHPI: improve C enum interopMarlon James2021-04-193-66/+113
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* VHPI: add tracingMarlon James2021-04-182-141/+706
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* Update license headerMarlon James2021-04-182-36/+19
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* vhdl: handle object interface using an interface type. Fix #1726Tristan Gingold2021-04-173-4/+56
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* vhdl-sem_names: avoid a crash for invalid user attribute prefix. Fix #1727Tristan Gingold2021-04-161-1/+2
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* synth: renaming (synth-heap -> synth-vhdl_heap)Tristan Gingold2021-04-165-11/+11
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* synth: renaming (synth-static_proc -> synth-vhdl_static_proc)Tristan Gingold2021-04-163-6/+6
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* synth: refactoring (synth.files_operations -> synth.vhdl_files)Tristan Gingold2021-04-166-11/+11
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* synth: renaming (synth.oper -> synth.vhdl_oper)Tristan Gingold2021-04-164-11/+11
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* synth: refactoring (synth.aggr -> synth.vhdl_aggr)Tristan Gingold2021-04-163-7/+7
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* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-1616-25/+25
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* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-152-0/+4
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* synth: avoid crash in case of non-elaboratable generic.Tristan Gingold2021-04-152-4/+10
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* vhdl-canon_psl: handle imp_boolTristan Gingold2021-04-151-2/+3
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* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-152-0/+2
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* trans-chap9: handle N_Imp_Bool for PSL. For #1721Tristan Gingold2021-04-131-0/+21
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* psl: suffix implication are properties (for simple subset). For #1721Tristan Gingold2021-04-133-6/+5
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* vhdl-sem_psl.adb: can also extract clock from SERE. For #1721Tristan Gingold2021-04-131-1/+5
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* vhdl-sem_names.adb: fix check for object prefix of subtype attribute. Fix #1717Tristan Gingold2021-04-111-3/+1
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* src: Clarify error for conditional signal assignment.Ondrej Ille2021-04-111-1/+2
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* src: Allow case generate only in VHDL 2008.Ondrej Ille2021-04-111-0/+1
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