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authorTristan Gingold <tgingold@free.fr>2021-05-07 19:20:32 +0200
committerTristan Gingold <tgingold@free.fr>2021-05-07 19:20:32 +0200
commit29aa770398bd26fb82f6322e887f8313de77f96f (patch)
tree1b15a0d1e7260e3284098d565292d47a19e3a217 /src
parent6266bf8c49ecf5d04d6de11b9d4d1064bbd84bcd (diff)
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synth-environment: add Set/Get_Kind, Wire_Unset
Diffstat (limited to 'src')
-rw-r--r--src/synth/synth-environment.adb21
-rw-r--r--src/synth/synth-environment.ads6
2 files changed, 26 insertions, 1 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index 001b417ca..9c9385dd4 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -69,6 +69,22 @@ package body Synth.Environment is
Wire_Rec.Kind := Wire_None;
end Free_Wire;
+ procedure Set_Kind (Wid : Wire_Id; Kind : Wire_Kind)
+ is
+ Wire_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
+ begin
+ pragma Assert (Kind = Wire_Unset or Wire_Rec.Kind = Wire_Unset);
+ Wire_Rec.Kind := Kind;
+ end Set_Kind;
+
+ function Get_Kind (Wid : Wire_Id) return Wire_Kind
+ is
+ Wire_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
+ begin
+ pragma Assert (Wire_Rec.Kind /= Wire_None);
+ return Wire_Rec.Kind;
+ end Get_Kind;
+
procedure Set_Wire_Gate (Wid : Wire_Id; Gate : Net) is
begin
-- Cannot override a gate.
@@ -974,7 +990,7 @@ package body Synth.Environment is
begin
case Wid_Rec.Kind is
when Wire_Signal | Wire_Output | Wire_Inout
- | Wire_Variable =>
+ | Wire_Variable | Wire_Unset =>
null;
when Wire_Input | Wire_Enable | Wire_None =>
raise Internal_Error;
@@ -1020,6 +1036,9 @@ package body Synth.Environment is
| Wire_Enable =>
-- For signals, always read the previous value.
return Wire_Rec.Gate;
+ when Wire_Unset =>
+ pragma Assert (Wire_Rec.Cur_Assign = No_Seq_Assign);
+ return Wire_Rec.Gate;
when Wire_None =>
raise Internal_Error;
end case;
diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads
index 70e472ac9..e06e254b2 100644
--- a/src/synth/synth-environment.ads
+++ b/src/synth/synth-environment.ads
@@ -78,6 +78,7 @@ package Synth.Environment is
Wire_Variable,
Wire_Enable,
Wire_Signal,
+ Wire_Unset,
Wire_Input, Wire_Output, Wire_Inout
);
@@ -87,6 +88,11 @@ package Synth.Environment is
-- Mark the wire as free.
procedure Free_Wire (Wid : Wire_Id);
+ -- Change wire WID kind.
+ -- The only allowed transitions are Unset <-> (Variable or Signal).
+ procedure Set_Kind (Wid : Wire_Id; Kind : Wire_Kind);
+ function Get_Kind (Wid : Wire_Id) return Wire_Kind;
+
-- Read and write the mark flag.
function Get_Wire_Mark (Wid : Wire_Id) return Boolean;
procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True);