| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | simul: handle more signals types | Tristan Gingold | 2022-09-15 | 2 | -23/+128 |
| * | trans-chap7: fix choice of exp. Fix #2189 | Tristan Gingold | 2022-09-15 | 1 | -3/+3 |
| * | ortho/mcode: add reg move for ret. Fix #2189 | Tristan Gingold | 2022-09-15 | 2 | -7/+17 |
| * | synth-vhdl_stmts: handle attribute names in expressions | Tristan Gingold | 2022-09-14 | 1 | -1/+3 |
| * | simul: handle --expect-failure for elaboration | Tristan Gingold | 2022-09-14 | 3 | -11/+15 |
| * | synth: detect overflow in static exponentiation | Tristan Gingold | 2022-09-14 | 5 | -76/+265 |
| * | synth: add bounds check for float-integer type conversion | Tristan Gingold | 2022-09-12 | 1 | -2/+21 |
| * | simul: factorize code for conversion functions | Tristan Gingold | 2022-09-12 | 1 | -19/+6 |
| * | simul: do not consider signal parameters as dynamic values | Tristan Gingold | 2022-09-12 | 3 | -1/+9 |
| * | synth: handle succ,pred,leftof,rightof attributes | Tristan Gingold | 2022-09-12 | 1 | -0/+95 |
| * | synth: improve handling of top-level interfaces subtype | Tristan Gingold | 2022-09-11 | 7 | -20/+58 |
| * | synth: initialize out parameters of procedures | Tristan Gingold | 2022-09-11 | 1 | -2/+9 |
| * | simul: move assertions (not to trigger in case of errors) | Tristan Gingold | 2022-09-11 | 1 | -3/+3 |
| * | simul: optimize resolution call only for std_logic | Tristan Gingold | 2022-09-11 | 1 | -5/+11 |
| * | synth: fix and add checks for memory management. | Tristan Gingold | 2022-09-10 | 16 | -116/+362 |
| * | simul: add support for protected objects | Tristan Gingold | 2022-09-08 | 12 | -23/+267 |
| * | elab-vhdl_objtypes: handle bounded array base type. Fix #2187 | Tristan Gingold | 2022-09-08 | 1 | -1/+2 |
| * | elab-vhdl_values: factorize code | Tristan Gingold | 2022-09-07 | 6 | -29/+16 |
| * | simul: do not propagate errors from resolution function | Tristan Gingold | 2022-09-07 | 1 | -0/+3 |
| * | synth-vhdl_stmts: fix handling of copyback parameters | Tristan Gingold | 2022-09-07 | 3 | -26/+38 |
| * | elab-vhdl_stmts: fix a TODO | Tristan Gingold | 2022-09-07 | 1 | -1/+3 |
| * | synth: handle open entity aspect | Tristan Gingold | 2022-09-07 | 1 | -4/+4 |
| * | elab-vhdl_heap: fix handling of simple access types | Tristan Gingold | 2022-09-07 | 1 | -4/+17 |
| * | simul: fix computation for number of drivers | Tristan Gingold | 2022-09-06 | 1 | -1/+2 |
| * | synth: handle generics in blocks | Tristan Gingold | 2022-09-06 | 4 | -10/+53 |
| * | simul: add an hook to display report/assert message | Tristan Gingold | 2022-09-06 | 3 | -50/+128 |
| * | synth-vhdl_eval: handle std_logic_signed and std_logic_unsigned | Tristan Gingold | 2022-09-06 | 1 | -55/+111 |
| * | synth: add evaluation for ieee.std_logic_arith | Tristan Gingold | 2022-09-05 | 6 | -43/+1181 |
| * | grt: add a SIGFPE handler for linux x86/64. Fix #2185 | Tristan Gingold | 2022-09-02 | 1 | -0/+4 |
| * | synth: extract synth-ieee-utils from synth-ieee-numeric_std | Tristan Gingold | 2022-09-02 | 2 | -21/+46 |
| * | synth: improve debug subprograms | Tristan Gingold | 2022-09-02 | 2 | -1/+8 |
| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 30 | -269/+981 |
| * | synth: factorize code for tracing statements execution | Tristan Gingold | 2022-09-02 | 4 | -16/+23 |
| * | simul: detect multiple drivers for unresolved signals | Tristan Gingold | 2022-09-02 | 1 | -8/+93 |
| * | simul-vhdl_simul: simplify procedure connect | Tristan Gingold | 2022-08-26 | 1 | -41/+22 |
| * | vhdl-sem_assocs: improve error message | Tristan Gingold | 2022-08-25 | 1 | -1/+1 |
| * | synth: handle component aspect configuration | Tristan Gingold | 2022-08-25 | 1 | -1/+5 |
| * | simul: handle connections of records | Tristan Gingold | 2022-08-25 | 1 | -1/+18 |
| * | synth: handle indexes/ranges in configurations for generate blocks | Tristan Gingold | 2022-08-25 | 2 | -5/+30 |
| * | synth: handle unbounded top-level ports | Tristan Gingold | 2022-08-25 | 1 | -9/+18 |
| * | synth: handle type left/right attributes | Tristan Gingold | 2022-08-25 | 3 | -0/+26 |
| * | simul: improve support of float signals | Tristan Gingold | 2022-08-24 | 1 | -3/+7 |
| * | grt-disp_signals: also disp conversions ranges | Tristan Gingold | 2022-08-24 | 1 | -0/+11 |
| * | simul: handle conversions and associations with constants | Tristan Gingold | 2022-08-24 | 2 | -70/+399 |
| * | simul: simplify code | Tristan Gingold | 2022-08-23 | 2 | -16/+7 |
| * | simul: factorize code to compute number of sources | Tristan Gingold | 2022-08-23 | 4 | -120/+50 |
| * | simul-vhdl_debug: disp nbr sources | Tristan Gingold | 2022-08-23 | 1 | -1/+15 |
| * | simul: add extra drivers for ports without sources | Tristan Gingold | 2022-08-23 | 3 | -14/+152 |
| * | elab: add default value to ports | Tristan Gingold | 2022-08-23 | 4 | -13/+28 |
| * | grt-signals: add ghdl_signal_add_extra_driver | Tristan Gingold | 2022-08-23 | 2 | -0/+19 |
