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* trans-chap7: Handle unbounded elements in Translate_ConcatenationTristan Gingold2021-09-071-27/+98
| | | | | Fix #1831 Fix #1657
* trans-chap3: add a stride parameter to index_array. For #1831Tristan Gingold2021-09-072-18/+21
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* vhdl/translate: adjust slice names for unbounded arrays. Fir #1836Tristan Gingold2021-09-033-4/+25
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* vhdl-scanner.adb: add commentsTristan Gingold2021-09-031-0/+6
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* vhdl,psl: abort is now identical to async_abort. For #1654Tristan Gingold2021-09-022-6/+4
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* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
| | | | For #1850
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
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* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-305-145/+255
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* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-3019-155/+306
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* vhdl-canon: detect PSL assertion that cannot fail. For #1832Tristan Gingold2021-08-292-3/+17
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* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
| | | | For #1832
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
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* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
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* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
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* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
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* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
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* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
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* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-282-1/+8
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* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
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* vhdl: handle foreign units in libraries and configurationTristan Gingold2021-08-283-24/+45
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* errorout: do not display empty linesTristan Gingold2021-08-283-1/+14
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* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
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* vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
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* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | For ghdl/ghdl-yosys-plugin#154
* std_names: add name keep.Tristan Gingold2021-08-272-1/+3
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* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
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* ghdlsynth.adb: fix a typoTristan Gingold2021-08-261-1/+1
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* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-269-11/+44
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* vhdl-evaluation: check integer evaluations fit in base type. Fix #1834Tristan Gingold2021-08-262-11/+37
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* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
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* ortho/gcc: adjust and propagate to all gcc versions the change for #1845Tristan Gingold2021-08-256-1/+81
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* vhdl-sem_types.adb: refine conditions for resolution functions.Tristan Gingold2021-08-251-3/+7
| | | | | | | Do not consider that functions with unbounded elements can be a resolution function. For #1844
* ghdldrv: handle auxbase option in ortho/gcc. Fix #1845Tristan Gingold2021-08-242-10/+16
| | | | | Remove additional option in ghdldrv.adb, automatically set aux_base_name in ortho-lang-9.c
* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-2422-463/+198
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* vhdl-sem_specs: avoid ownership issue on default map aspect.Tristan Gingold2021-08-241-1/+4
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* Rework inertial associations.Tristan Gingold2021-08-238-46/+228
| | | | | Fix #1625 Fix #1672
* trans-chap3: handle (ignore) use clauses in protected types. Fix #1833Tristan Gingold2021-08-141-1/+2
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-0617-392/+482
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* trans-chap7: handle strings in static array. Fix #1637Tristan Gingold2021-08-061-2/+2
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* vhdl-sem_expr.adb: check matching subtype of array aggregate elements.Tristan Gingold2021-08-061-31/+67
| | | | | When the subtype of the aggregate is not known by the context. Fix #1723
* trans-chap3: do not create same range_var for enumeration subtype.Tristan Gingold2021-08-061-27/+41
| | | | | | As there is not ranges for enumerated type, a range_var was always created for subtypes of enumerated types even if they had the same range. Create the range_var for bool types.
* vhdl: adjust ownership of agrgegate element subtypes. Fix #1419Tristan Gingold2021-08-052-14/+31
| | | | | Disable transfer of array aggregate element subtype ownership, but create the info of aggregate element subtype.
* vhdl-sem_expr: add commentsTristan Gingold2021-08-041-0/+6
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* vhdl-sem_expr: check subtype constraint of record aggregate elements.Tristan Gingold2021-08-041-1/+2
| | | | For #1419
* vhdl-disp_tree: disp integer literal valueTristan Gingold2021-08-041-15/+27
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* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-033-13/+164
| | | | | | | | In case of array aggregate whose element subtype is not bounded, extract it from the aggregate elements. Fix #1055 Fix #1455
* ghdldrv.adb: use cc (instead of gcc) as linker driver. Fix #1629Tristan Gingold2021-08-011-1/+1
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* vhdl-parse: use if_generate_else_clause for elsif clauses. Fix #1824Tristan Gingold2021-07-291-1/+1
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