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* trans-chap12: refactor.Tristan Gingold2016-03-072-53/+70
* translate: separate decl and stmt elab subprograms.Tristan Gingold2016-02-236-96/+319
* translate: minor reformating.Tristan Gingold2016-02-211-24/+19
* grt: remove rti field in signals (to reduce space).Tristan Gingold2016-02-211-1/+0
* ortho: rename start/finish_const_value to start/finish_init_value.Tristan Gingold2016-02-218-64/+64
* trans-chap12: factorize code.Tristan Gingold2016-02-201-9/+1
* Refactoring in simulate in order to link with ortho.Tristan Gingold2016-02-2016-1213/+1307
* parse: detect early use of signature in expressions.Tristan Gingold2016-02-181-1/+8
* parse: avoid weird error message for end protected.Tristan Gingold2016-02-171-1/+8
* assocations: check rules for unconstrained formal (LRM08 5.3.2.2 e 3)Tristan Gingold2016-02-172-4/+39
* Tentative fix for issue43.Tristan Gingold2016-02-171-1/+1
* Fix crash of issue42.Tristan Gingold2016-02-171-1/+2
* simul debugger: add info instancesTristan Gingold2016-02-172-3/+46
* psl: cover directive works on a sequence, not on a property.Tristan Gingold2016-02-171-2/+0
* PSL: move canon code to canon.adbTristan Gingold2016-02-171-0/+2
* simul: fix local protected object, boolean for-generate loopTristan Gingold2016-02-143-38/+51
* simul debugger: handle more concurrent statements.Tristan Gingold2016-02-141-0/+50
* simul: more fixes for std_ulogic.Tristan Gingold2016-02-142-17/+21
* psl: cover directive works on a sequence, not on a property.Tristan Gingold2016-02-1416-78/+292
* simul: preliminary work to support PSL.Tristan Gingold2016-02-147-105/+323
* PSL: move canon code to canon.adbTristan Gingold2016-02-147-135/+308
* simul: return the exit status set by std.envTristan Gingold2016-02-141-2/+4
* simul: check for no unconstrained port/generic of top-level entity.Tristan Gingold2016-02-142-1/+30
* simul: make delayed signal elaborated.Tristan Gingold2016-02-101-0/+1
* simul: add support of e8.Tristan Gingold2016-02-109-170/+205
* simul: handle generic override.Tristan Gingold2016-02-103-20/+106
* evaluation: handle whitespace for 'value.Tristan Gingold2016-02-103-1/+54
* build_enumeration_value: correctly handle characters.Tristan Gingold2016-02-101-12/+22
* simul: handle slice in individual association for subprograms.Tristan Gingold2016-02-101-0/+11
* simul: fix type conversion to unconstrained array.Tristan Gingold2016-02-101-14/+35
* simul: fix corner cases for image.Tristan Gingold2016-02-101-100/+131
* simul: fix issue14.Tristan Gingold2016-02-101-10/+21
* simul: fix elaboration check for implicit signals.Tristan Gingold2016-02-101-0/+1
* simul: fix individual association for array.Tristan Gingold2016-02-091-3/+4
* simul: add missing canon.Tristan Gingold2016-02-091-3/+3
* simul: avoid stupid crashes in debugger.Tristan Gingold2016-02-091-2/+10
* PSL: handle and/or in boolean assertion.Tristan Gingold2016-02-093-19/+66
* Improve mixed dump of PSL and VHDL nodes.Tristan Gingold2016-02-092-14/+16
* A subtype of a resolved array type is resolved.Tristan Gingold2016-02-061-0/+3
* simul: handle vhdl 2008.Tristan Gingold2016-02-0610-164/+358
* simul: support of package instantiation.Tristan Gingold2016-02-064-11/+85
* sem_inst: add a comment.Tristan Gingold2016-02-061-0/+2
* simul: preliminary work for environments.Tristan Gingold2016-01-276-80/+57
* translation: use Tables instead of GNAT.Table.Tristan Gingold2016-01-271-4/+3
* simul: use Tables instead of GNAT.TableTristan Gingold2016-01-275-36/+24
* simul: handle declarations in configuration.Tristan Gingold2016-01-273-59/+68
* simul: fix attribute specification, noop type conversion, indiv sig assoc.Tristan Gingold2016-01-265-11/+37
* Fix check of conformance for physical units.Tristan Gingold2016-01-251-1/+4
* simul: handle default assignment to unconstrained ports.Tristan Gingold2016-01-243-109/+63
* Avoid a crash in physical type definition.Tristan Gingold2016-01-242-49/+57
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