| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: preliminary work to support intrinsic procedures. | Tristan Gingold | 2019-11-14 | 2 | -0/+26 |
| * | synth: file support (WIP). | Tristan Gingold | 2019-11-12 | 1 | -1/+2 |
| * | synth: initial support for file types. For #1004 | Tristan Gingold | 2019-11-11 | 1 | -27/+33 |
| * | synth: initial support of access type. For #1004 | Tristan Gingold | 2019-11-11 | 1 | -0/+4 |
| * | vhdl-ieee-std_logic_1164: minor simplification. | Tristan Gingold | 2019-11-06 | 1 | -21/+8 |
| * | synth: handle edge operators in synth_predefined_function_call. | Tristan Gingold | 2019-11-06 | 2 | -5/+4 |
| * | vhdl: recognize rising_edge/falling_edge. | Tristan Gingold | 2019-11-06 | 2 | -6/+15 |
| * | vhdl-scanner: handle 'synopsys' pragma. | Tristan Gingold | 2019-11-04 | 1 | -1/+2 |
| * | vhdl-prints: handle more constructs in psl vunit. | Tristan Gingold | 2019-10-31 | 1 | -0/+5 |
| * | vhdl: allow attributes in vunit declarations. | Tristan Gingold | 2019-10-30 | 6 | -200/+216 |
| * | synth: handle concurrent signal assignment in vunits. | Tristan Gingold | 2019-10-25 | 1 | -0/+2 |
| * | vhdl-canon: handle simple signal assignment in vunits. | Tristan Gingold | 2019-10-25 | 1 | -273/+272 |
| * | vhdl-canon: extract canon_concurrent_label. | Tristan Gingold | 2019-10-25 | 1 | -20/+25 |
| * | vhdl-annotations: extract annotate_concurrent_statement. | Tristan Gingold | 2019-10-25 | 1 | -47/+53 |
| * | vhdl-annotations: minor renaming. | Tristan Gingold | 2019-10-25 | 1 | -8/+8 |
| * | vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits. | Tristan Gingold | 2019-10-25 | 4 | -119/+122 |
| * | vhdl-parse_psl: add comments. | Tristan Gingold | 2019-10-25 | 1 | -8/+71 |
| * | vhdl-parse: do not scan PSL keywords in vunit declarations. | Tristan Gingold | 2019-10-24 | 1 | -0/+4 |
| * | vhdl/translate: elaborate dependencies of configurations. Fix #984 | Tristan Gingold | 2019-10-24 | 1 | -0/+4 |
| * | vhdl-prints: do not crash on vunit declarations. | Tristan Gingold | 2019-10-23 | 1 | -0/+4 |
| * | vhdl-annotations: handle some declarations in vunits. | Tristan Gingold | 2019-10-23 | 1 | -0/+6 |
| * | vhdl-canon: handle some declarations in vunits. | Tristan Gingold | 2019-10-23 | 1 | -2/+18 |
| * | vhdl-sem_psl: analyze some declarations. | Tristan Gingold | 2019-10-23 | 1 | -0/+18 |
| * | vhdl-sem_decls: make sem_declaration public. | Tristan Gingold | 2019-10-23 | 5 | -14/+31 |
| * | vhdl-sem_decls: extract sem_declaration. | Tristan Gingold | 2019-10-23 | 1 | -121/+118 |
| * | vhdl-sem_decls: add comment. | Tristan Gingold | 2019-10-21 | 1 | -0/+3 |
| * | vhdl-parse: parse declarations in vunit. | Tristan Gingold | 2019-10-21 | 1 | -327/+352 |
| * | vhdl: handle labels in verification units. | Tristan Gingold | 2019-10-21 | 1 | -8/+62 |
| * | psl: add active state. | Tristan Gingold | 2019-10-21 | 1 | -0/+7 |
| * | vhdl-prints: handle restrict in vunit. | Tristan Gingold | 2019-10-21 | 1 | -0/+2 |
| * | vhdl: try to convert identifier to token only for identifiers | Tristan Gingold | 2019-10-20 | 1 | -1/+3 |
| * | vhdl-prints: add parenthesis around boolean and/or. | Tristan Gingold | 2019-10-18 | 1 | -0/+4 |
| * | vhdl: check cover/restrict is followed by a sequence. | Tristan Gingold | 2019-10-16 | 4 | -11/+65 |
| * | vhdl: Add the implicit [*] at start of PSL cover sequence. | Tristan Gingold | 2019-10-15 | 1 | -0/+7 |
| * | vhdl: handle cover and restrict within vunit. | Tristan Gingold | 2019-10-15 | 4 | -1/+15 |
| * | vhdl-evaluation: handle bit condition operator. Fix #977 | Tristan Gingold | 2019-10-13 | 1 | -0/+3 |
| * | vhdl-annotations: handle list of record elements declaration. | Tristan Gingold | 2019-10-13 | 1 | -2/+4 |
| * | vhdl: recognize std_logic_unsigned.conv_integer. | Tristan Gingold | 2019-10-13 | 2 | -0/+7 |
| * | vhdl: recognize conv_integer functions from std_logic_arith. | Tristan Gingold | 2019-10-11 | 2 | -18/+30 |
| * | vhdl: recognize std_logic_signed package (from synopsys). | Tristan Gingold | 2019-10-11 | 4 | -14/+64 |
| * | vhdl: recognize minus from std_logic_unsigned | Tristan Gingold | 2019-10-11 | 2 | -0/+15 |
| * | vhdl: do not try to recognize mentor version of std_logic_arith. | Tristan Gingold | 2019-10-10 | 1 | -0/+7 |
| * | vhdl: recognize conv_unsigned from ieee.std_logic_arith. | Tristan Gingold | 2019-10-10 | 4 | -1/+201 |
| * | synth: handle package bodies. | Tristan Gingold | 2019-10-07 | 1 | -0/+1 |
| * | vhdl: recognize to_bitvector. | Tristan Gingold | 2019-10-07 | 2 | -81/+74 |
| * | synth: add support for concurrent procedure calls. Fix #969 | Tristan Gingold | 2019-10-07 | 1 | -1/+2 |
| * | Rework errors handling, to have a more generic framework. | Tristan Gingold | 2019-10-06 | 2 | -4/+61 |
| * | synth: improve support of arrays or arrays. Fix #955 | Tristan Gingold | 2019-10-01 | 1 | -13/+8 |
| * | vhdl: recognize div operators. | Tristan Gingold | 2019-09-30 | 2 | -0/+27 |
| * | vhdl-std_package: reduce cascaded error messages. | Tristan Gingold | 2019-09-30 | 1 | -0/+1 |
