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vhdl
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Author
Age
Files
Lines
*
Display a nice message if std_logic_textio is not found.
Tristan Gingold
2016-08-27
1
-0
/
+4
*
Avoid crash on invalid selection of a procedure.
Tristan Gingold
2016-08-26
2
-3
/
+10
*
Also consider 'not' for non-psl assert statement.
Tristan Gingold
2016-08-26
1
-1
/
+1
*
Avoid redudant quote in error message
Tristan Gingold
2016-08-26
1
-2
/
+0
*
Avoid a crash on bad component name.
Tristan Gingold
2016-08-26
3
-6
/
+20
*
evaluation: factorize code, rewrite an error message.
Tristan Gingold
2016-08-25
1
-12
/
+4
*
Rewrite most of error and warning messages.
Tristan Gingold
2016-08-02
15
-107
/
+165
*
Rewrite error messages.
Tristan Gingold
2016-08-02
22
-917
/
+897
*
Rewrite scan error messages: use formatting.
Tristan Gingold
2016-08-02
17
-241
/
+456
*
Rework warnings to have a uniq tag per warning.
Tristan Gingold
2016-08-01
16
-104
/
+263
*
sem_expr: minor rework.
Tristan Gingold
2016-07-30
1
-3
/
+2
*
Add comment.
Tristan Gingold
2016-07-30
1
-1
/
+7
*
Improve handling of direction in aggregate.
Tristan Gingold
2016-07-30
1
-5
/
+15
*
Fix translation of leftof/rightof.
Tristan Gingold
2016-07-30
1
-2
/
+4
*
Allow alias of literals in strings.
Tristan Gingold
2016-07-30
2
-6
/
+22
*
Improve error message if synopsys package it not found.
Tristan Gingold
2016-07-18
1
-3
/
+23
*
sem: handle case-generate in block configuration.
Tristan Gingold
2016-07-17
1
-2
/
+55
*
ghdldrv: add --bootstrap-standard to simplify build.
Tristan Gingold
2016-07-15
1
-1
/
+3
*
Clean up links, repository-wide (#117)
Ben Wiederhake
2016-07-09
1
-1
/
+1
*
Adjust xrefs for case-generate and context declaration.
Tristan Gingold
2016-07-07
1
-3
/
+9
*
disp_vhdl: support context declaration and reference
Tristan Gingold
2016-07-07
1
-7
/
+39
*
vhdl08: add support of case-generate statement
Tristan Gingold
2016-07-07
16
-231
/
+693
*
Parse case generate statement.
Tristan Gingold
2016-07-05
6
-79
/
+269
*
parse: extract parse_case_statement.
Tristan Gingold
2016-07-05
2
-84
/
+101
*
Fix indentation and English mistakes.
Tristan Gingold
2016-07-05
24
-101
/
+92
*
A package instantiation does not depend on the body if it is not required.
Tristan Gingold
2016-07-03
1
-4
/
+6
*
vhdl08: fix parse of elsif in generate.
Tristan Gingold
2016-07-03
1
-9
/
+31
*
Enable vest recursive instantiation test.
Tristan Gingold
2016-07-03
3
-8
/
+23
*
Initial support of direct recursive instantiation.
Tristan Gingold
2016-07-03
13
-400
/
+605
*
Handle uninstantiated packages without body.
Tristan Gingold
2016-06-28
2
-14
/
+38
*
trans-chap4: remove a when others.
Tristan Gingold
2016-06-28
1
-4
/
+2
*
simulate/execution: uses grt.strings
Tristan Gingold
2016-06-28
1
-5
/
+6
*
Handle default parameters for file_open.
Tristan Gingold
2016-06-02
4
-7
/
+22
*
Remove Get/Set_Type_Reference
Tristan Gingold
2016-06-01
6
-217
/
+166
*
vhdl2008: implement new 'use clause' rules for types.
Tristan Gingold
2016-05-31
10
-231
/
+444
*
Individual association: fix crash for array conversion due to slice.
Tristan Gingold
2016-05-27
1
-0
/
+6
*
Minor cleanup.
Tristan Gingold
2016-03-31
1
-9
/
+0
*
simulation: remove unused kind_range.
Tristan Gingold
2016-03-29
2
-9
/
+1
*
Avoid a crash on error.
Tristan Gingold
2016-03-26
5
-91
/
+73
*
Adjust previous patch (detect incorrect use of PSL endpoint in expressions)
Tristan Gingold
2016-03-23
3
-167
/
+171
*
PSL: add clocked SERE, make endpoints visible from VHDL.
Tristan Gingold
2016-03-22
17
-237
/
+423
*
Create psl_endpoint_declaration.
Tristan Gingold
2016-03-20
4
-169
/
+226
*
wip.
Tristan Gingold
2016-03-20
1
-1
/
+3
*
PSL: add counters, generate rti and add --psl-report
Tristan Gingold
2016-03-18
4
-57
/
+66
*
PSL translate: handle bit type.
Tristan Gingold
2016-03-18
1
-4
/
+8
*
translation: avoid memory leak while allocating ports.
Tristan Gingold
2016-03-16
4
-18
/
+36
*
trans-chap12: extract gen_stubs from write_list_list.
Tristan Gingold
2016-03-11
2
-13
/
+54
*
simulation: reuse Mode_Signal_Type from grt.types.
Tristan Gingold
2016-03-10
5
-72
/
+76
*
elaboration: use std_time to represent time in signal table.
Tristan Gingold
2016-03-10
3
-9
/
+9
*
simulation: add block id.
Tristan Gingold
2016-03-10
3
-1
/
+13
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