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path: root/src/vhdl/vhdl-prints.adb
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* vhdl-prints: handle suspend state declarations and statementsTristan Gingold2023-01-101-2/+22
* vhdl-parse: handle 'end for' in configuration specification.Tristan Gingold2022-12-211-0/+9
* vhdl: rework comment gathering to handle empty lines.Tristan Gingold2022-11-271-0/+2
* vhdl-prints: add an option to display commentsTristan Gingold2022-11-201-0/+46
* vhdl-prints: improve handling of PSL. For #2178Tristan Gingold2022-08-151-5/+75
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-1/+4
* vhdl-prints: handle default in interface subprogramTristan Gingold2022-08-071-1/+19
* vhdl-prints.adb: avoid crash on PSL endpointsTristan Gingold2022-08-041-3/+12
* vhdl-prints: improve outputTristan Gingold2022-08-031-2/+22
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-1/+1
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-3/+15
* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-261-0/+4
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-25/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-2/+3
* psl: prefix of goto/non-consecutive repetition is a bool. Fix #1708Tristan Gingold2021-04-031-8/+15
* Add base support for the attribue element in vhdl 08Anselmo952021-04-031-0/+2
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+20
* update license headersumarcor2021-01-141-11/+9
* vhdl-formatters: add realignmentTristan Gingold2021-01-111-1/+12
* vhdl: rework formatter engine, add 'ghdl fmt' commandTristan Gingold2021-01-091-2/+1
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-16/+20
* vhdl-prints: avoid assertion on empty hbox for simple loopTristan Gingold2021-01-041-7/+16
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+31
* Synthesis of PSL built-in fell() function.tmeissner2020-06-071-0/+17
* Synthesis of PSL built-in rose() function.tmeissner2020-06-061-0/+17
* Synthesis of PSL stable() function.tmeissner2020-06-061-0/+17
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-1/+25
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-1/+1
* vhdl-prints: handle evaluated expression for qualified_expression.Tristan Gingold2020-04-181-16/+19
* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
* vhdl-prints: disable code to display anonymous signal.Tristan Gingold2020-03-021-2/+10
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+2
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-8/+7
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-40/+89
* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-301-0/+2
* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-1/+36
* ams-vhdl: print subnature declarations.Tristan Gingold2019-12-301-1/+16
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-127/+405
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+2
* vhdl-prints: subtype indication is optional in object alias.Tristan Gingold2019-12-261-3/+2
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
* psl: add active state.Tristan Gingold2019-10-211-0/+7
* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+4
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-201-1/+1
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
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