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* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+17
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+2
* update license headersumarcor2021-01-141-11/+9
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-0/+32
* Rework initialization and finalization.Tristan Gingold2020-12-301-1/+5
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-0/+16
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-2/+2
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+18
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+39
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-9/+8
* vhdl-nodes: reduce size of Iterator_Declaration.Tristan Gingold2020-07-011-3/+3
* vhdl-nodes: add Open_Flag to all generic interfaces.Tristan Gingold2020-06-261-2/+2
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-4/+20
* Synthesis of PSL prev function.Tristan Gingold2020-06-021-8/+8
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+52
* vhdl-nodes: use a flag field for direction.Tristan Gingold2020-05-201-2/+7
* vhdl: allow attribute specifications in protected types. For #1252Tristan Gingold2020-04-201-22/+22
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-4/+4
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-0/+35
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+16
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+1
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-1/+36
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+2
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-0/+16
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-13/+391
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+16
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+32
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-9/+9
* synth: handle verification units.Tristan Gingold2019-08-201-1/+17
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-2/+3
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-3/+54
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-16/+0
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+2
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+1
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+1
* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-0/+16
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-18/+2
* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-10/+33
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-26/+26
* Make lists a generic package, add vhdl-lists.Tristan Gingold2019-05-091-1/+1
* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-061-1/+1
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-0/+6569