iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth-vhdl_eval: handle to_X01 for bit to std_ulogic.	Tristan Gingold	2023-01-11	1	-0/+27
*	vhdl: recognize ieee.math_real.sign, fix is_x recogn.	Tristan Gingold	2022-06-11	1	-4/+16
*	vhdl: recognize more predefined ieee functions and operators	Tristan Gingold	2022-06-05	1	-0/+7
*	vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostring	Tristan Gingold	2022-06-01	1	-0/+4
*	update license headers	umarcor	2021-01-14	1	-11/+9
*	vhdl: recognize logica vec/log and log/vec operators. For #1520	Tristan Gingold	2020-12-03	1	-0/+82
*	vhdl: replace base_type with parent_type in nodes	Tristan Gingold	2020-07-22	1	-0/+1
*	vhdl: decode to_x01 (from ieee.std_logic_1164)	Tristan Gingold	2020-06-19	1	-0/+7
*	synth: handle reduction operators. Fix #1342	Tristan Gingold	2020-05-27	1	-4/+10
*	synth-oper: recognize more operations from std_logic_arith.	Tristan Gingold	2020-04-12	1	-0/+2
*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	1	-0/+43
*	synth: handle some rotation and shifts. Fix #1077	Tristan Gingold	2020-01-30	1	-0/+44
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	1	-0/+6
*	vhdl-ieee-std_logic_1164: minor simplification.	Tristan Gingold	2019-11-06	1	-21/+8
*	synth: handle edge operators in synth_predefined_function_call.	Tristan Gingold	2019-11-06	1	-3/+4
*	vhdl: recognize rising_edge/falling_edge.	Tristan Gingold	2019-11-06	1	-6/+12
*	vhdl: recognize to_bitvector.	Tristan Gingold	2019-10-07	1	-81/+72
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	1	-5/+15
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	1	-5/+18
*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-1/+1
*	vhdl: move ieee packages to vhdl children.	Tristan Gingold	2019-05-05	1	-0/+319