| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: fix handling of subtype indication in object aliases for vhdl 2008. | Tristan Gingold | 2020-03-29 | 1 | -1/+4 |
| * | synth: avoid crash on bad elaboration order. | Tristan Gingold | 2020-03-09 | 1 | -1/+3 |
| * | synth: handle deferred constants. Fix #1096 | Tristan Gingold | 2020-01-16 | 1 | -0/+3 |
| * | synth: support multiple synthesis. | Tristan Gingold | 2019-12-02 | 1 | -0/+28 |
| * | synth: file support (WIP). | Tristan Gingold | 2019-11-12 | 1 | -1/+2 |
| * | synth: initial support for file types. For #1004 | Tristan Gingold | 2019-11-11 | 1 | -27/+33 |
| * | synth: initial support of access type. For #1004 | Tristan Gingold | 2019-11-11 | 1 | -0/+4 |
| * | vhdl: allow attributes in vunit declarations. | Tristan Gingold | 2019-10-30 | 1 | -1/+3 |
| * | synth: handle concurrent signal assignment in vunits. | Tristan Gingold | 2019-10-25 | 1 | -0/+2 |
| * | vhdl-annotations: extract annotate_concurrent_statement. | Tristan Gingold | 2019-10-25 | 1 | -47/+53 |
| * | vhdl-annotations: minor renaming. | Tristan Gingold | 2019-10-25 | 1 | -8/+8 |
| * | vhdl-annotations: handle some declarations in vunits. | Tristan Gingold | 2019-10-23 | 1 | -0/+6 |
| * | vhdl: handle cover and restrict within vunit. | Tristan Gingold | 2019-10-15 | 1 | -1/+3 |
| * | vhdl-annotations: handle list of record elements declaration. | Tristan Gingold | 2019-10-13 | 1 | -2/+4 |
| * | synth: add support for concurrent procedure calls. Fix #969 | Tristan Gingold | 2019-10-07 | 1 | -1/+2 |
| * | synth: handle record subtypes. | Tristan Gingold | 2019-09-19 | 1 | -5/+8 |
| * | vhdl-annotations: ignore conditional variable assignment. | Tristan Gingold | 2019-08-30 | 1 | -1/+2 |
| * | vhdl-annotate: handle shared anonymous subtype in interfaces. | Tristan Gingold | 2019-08-30 | 1 | -1/+4 |
| * | synth: add support for record types. | Tristan Gingold | 2019-08-29 | 1 | -0/+4 |
| * | synth: support sequential conditional signal assignment. | Tristan Gingold | 2019-08-27 | 1 | -0/+1 |
| * | vhdl: handle assume in verification units. | Tristan Gingold | 2019-08-20 | 1 | -1/+2 |
| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -1/+29 |
| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 |
| * | synth: improve support of vhdl08. Fix #882 | Tristan Gingold | 2019-08-05 | 1 | -1/+9 |
| * | synth: unconstrained arrays. | Tristan Gingold | 2019-07-28 | 1 | -0/+3 |
| * | synth: preliminary support of dynamic indexing. | Tristan Gingold | 2019-07-28 | 1 | -45/+66 |
| * | vhdl annotations: fix annotation of type in interface list. | Tristan Gingold | 2019-07-24 | 1 | -0/+1 |
| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 1 | -5/+8 |
| * | synth: do not crash on use of std_logic_1164 2008. | Tristan Gingold | 2019-07-10 | 1 | -10/+4 |
| * | vhdl-annotations: partial revert of previous patch for | Tristan Gingold | 2019-07-04 | 1 | -0/+10 |
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 |
| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+2 |
| * | synth: handle vhdl2008 std_logic_1164, handle anonymous_signal. | Tristan Gingold | 2019-07-04 | 1 | -2/+2 |
| * | vhdl: translate anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+2 |
| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -1/+2 |
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -0/+1315 |
