iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	translate: separate decl and stmt elab subprograms.	Tristan Gingold	2016-02-23	1	-22/+195
*	translate: minor reformating.	Tristan Gingold	2016-02-21	1	-24/+19
*	Tentative fix for issue43.	Tristan Gingold	2016-02-17	1	-1/+1
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-1/+7
*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-14	1	-50/+26
*	Pass signal values to interfaces. 'sigptr' optimization.	Tristan Gingold	2015-12-18	1	-2/+6
*	Suppress stack switching; save process state in secondary stack.	Tristan Gingold	2015-09-04	1	-0/+29
*	Translate: explicitly clean transient types.	Tristan Gingold	2015-09-02	1	-1/+5
*	Allow allocators in default value of subprograms	Tristan Gingold	2015-08-29	1	-48/+116
*	Replace fat accesses by bounds accesses	Tristan Gingold	2015-08-29	1	-37/+32
*	Rework procedure calls, now use a record to pass parameters.	Tristan Gingold	2015-06-05	1	-2/+1
*	Fix entity instantiation with extended identifier.	Tristan Gingold	2015-03-31	1	-3/+5
*	Keep and handle simple name for Block_Specification.	Tristan Gingold	2015-01-16	1	-2/+2
*	Fix ticket #29: add instance label in created symbols name.	Tristan Gingold	2015-01-11	1	-1/+3
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-177/+249
*	Rework for vhdl08 generate: change rtis.	Tristan Gingold	2015-01-04	1	-1/+2
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-71/+97
*	trans-chap9: fix invalid generation of ortho code.	Tristan Gingold	2014-11-20	1	-4/+5
*	Split translation into child packages.	Tristan Gingold	2014-11-09	1	-0/+1953