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* simul: handle interface type.Tristan Gingold2017-12-072-3/+6
* simul: handle generic-mapped packages.Tristan Gingold2017-12-071-4/+11
* simul: handle nested package instantiation.Tristan Gingold2017-12-072-2/+5
* simul: fix execution of actual expression.Tristan Gingold2017-12-063-13/+40
* simul: remove Current_Component (unused).Tristan Gingold2017-12-062-11/+3
* simul: fix choice list for case generate statement.Tristan Gingold2017-12-051-2/+4
* simul: fix elaboration check for package.Tristan Gingold2017-12-051-1/+5
* simul: handle unconstrained case choice.Tristan Gingold2017-12-051-1/+17
* simul: psl default clock, unaffected waveform.Tristan Gingold2017-12-053-0/+8
* simul: handle interface subprogram.Tristan Gingold2017-12-053-11/+26
* simul: handle package interface, remove iir_value_environment.Tristan Gingold2017-12-059-80/+25
* simul: handle instantiated package.Tristan Gingold2017-12-054-11/+46
* simul: add support for case generate statetement.Tristan Gingold2017-12-044-14/+68
* simul: support nested packages.Tristan Gingold2017-12-042-58/+71
* simul: WIP for nested packages.Tristan Gingold2017-12-042-3/+7
* simul: add iir_value_instance, remove package_instances.Tristan Gingold2017-12-038-35/+81
* simul: Remove scope_type (unused).Tristan Gingold2017-12-034-186/+14
* simul: add global_info.Tristan Gingold2017-12-036-63/+77
* simul: refactoring: scope is now the corresponding sim_info.Tristan Gingold2017-12-038-112/+119
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-2423-77/+97
* simulation: refactoring (move block_instance to iir_values).Tristan Gingold2017-11-2411-117/+113
* Annotations: minor reformating.Tristan Gingold2017-11-192-24/+15
* ghdl_simul: handle obsoleted and optionnal package body.Tristan Gingold2017-11-181-2/+14
* ghdl_simul: use target bounds for variable assignment of an aggregate.Tristan Gingold2017-11-181-3/+1
* ghdl_simul: fix crash in elaboration.Tristan Gingold2017-11-181-10/+7
* simulate: add per signal id.Tristan Gingold2017-11-163-2/+20
* simulate: add port map.Tristan Gingold2017-11-163-16/+29
* simulate: add extra_slot.Tristan Gingold2017-11-162-7/+22
* list: update simulator.Tristan Gingold2017-11-113-30/+31
* Update simulate.Tristan Gingold2017-11-087-79/+67
* simulate: update (and revive).Tristan Gingold2017-10-246-33/+87
* ghdl_simul: also renames conversion.Tristan Gingold2017-09-133-9/+27
* Fix build error for ghdlsynth.Tristan Gingold2017-05-091-1/+1
* simulate: reorder block list, support Concurrent_Simple_Signal_AssignmentTristan Gingold2017-01-314-25/+60
* Fix ghdlsimul build.Tristan Gingold2017-01-312-4/+5
* ownership: fix ghdlsimulTristan Gingold2016-12-124-29/+56
* simulation: remove sim_be after previous code factorization.Tristan Gingold2016-10-155-199/+61
* Rework AST to setup ownership and reference policy.Tristan Gingold2016-10-112-4/+2
* Rewrite most of error and warning messages.Tristan Gingold2016-08-022-13/+14
* Rewrite error messages.Tristan Gingold2016-08-021-4/+3
* Rewrite scan error messages: use formatting.Tristan Gingold2016-08-022-9/+10
* Rework warnings to have a uniq tag per warning.Tristan Gingold2016-08-011-1/+2
* Fix indentation and English mistakes.Tristan Gingold2016-07-051-3/+3
* simulate/execution: uses grt.stringsTristan Gingold2016-06-281-5/+6
* simulation: remove unused kind_range.Tristan Gingold2016-03-292-9/+1
* simulation: reuse Mode_Signal_Type from grt.types.Tristan Gingold2016-03-105-72/+76
* elaboration: use std_time to represent time in signal table.Tristan Gingold2016-03-103-9/+9
* simulation: add block id.Tristan Gingold2016-03-103-1/+13
* simul debugger: display packages and configuration.Tristan Gingold2016-03-101-2/+12
* Refactoring in simulate in order to link with ortho.Tristan Gingold2016-02-2012-1213/+1206
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